Voltage Down Converters (VDCs) are used to lower the level of an external power supply voltage (e.g., Vddq) provided to a semiconductor device to a desired internal power supply voltage (e.g., Vdd). For example, a voltage down converter in a semiconductor integrated circuit may lower an external power supply voltage to the level of an internal power supply voltage, so that each component element within the integrated circuit may be operated with the internal power supply voltage to reduce power consumption and secure sufficient reliability of each component element. Another use of the VDC in the area of high-speed memory devices such as dynamic random access memories (DRAM), is the generation of a substantially constant high supply voltage that is greater than the logic “1” voltage level stored in a memory cell.
A fast voltage down converter can be used as a substantially constant high voltage supply for providing a power supply voltage (e.g., Vpp) to the memory device. This is particularly important within high speed embedded memory devices having small die area available on a system-on-a-chip (SOC) application. When the die area is small, i.e. in an embedded memory implementation, there is inadequate capacitive loading on a high voltage supply output in order to store the charge necessary to maintain a substantially constant supply voltage. Moreover, the operating frequency of current memory devices now exceeds 800 MHz in most leading edge embedded memory applications. A fast response of the voltage down converter is an important factor in providing a substantially constant high supply voltage Vpp to the memory. The stability of the substantially constant high supply voltage Vpp during the different modes of operation of the memory, greatly depends on the capacitive loading and the reservoir capacitance of the voltage supply output. The capacitive loading is created by the sum of all elements having an inherent capacitance (for example transistor gates) that are mutually connected to the Vpp output node.
The reservoir capacitance is typically a separate dedicated large capacitance that is connected to the Vpp output to provide further capacitive loading and stability on the output in addition to the inherent aforementioned capacitive loading on the Vpp output. However, the small size of embedded memory devices creates some problems of stability in the required internal level supply. Active operations that take place in the memory, i.e. read, write and/or refresh operations, contribute to create a ripple effect on the voltage level Vpp given the current load that such operations provide. The voltage ripple level is affected by the total capacitance such thatVripple˜ILOAD*T/(CLOAD+CRESERVOIR),where ILOAD is the leakage or operating current and CLOAD is the total loading of the Vpp voltage. Since the load and reservoir capacitances are small in embedded memory applications, the ripple voltage level becomes very dependent on fluctuations in load current, which can occur based on different current loading scenarios. Because of this problem, embedded memories experience significant voltage supply fluctuation.
The common solution for this fluctuation problem has been to insert as large a reservoir capacitor as possible in order to hold the voltage level provided by the voltage down-converter VDC as stable as possible. One such conventional solution 100 is shown in FIG. 1A. However, a key issue of embedded memory is their small size that does not allow adequate space in order to place such a large reservoir capacitor. In such instance as in FIG. 1A, either CLOAD or CM would have to be adjusted to be a very high capacitance in order to provide the necessary stability for the voltage-down conversion. Because CLOAD represents the whole memory array and such arrays are becoming increasingly smaller, the result is that CM would need to be increased significantly. However, increasing CM results in an increased penalty area that, in the case of embedded applications, is one of the major design constraints.
An alternative approach as shown in a prior art voltage down converter FIG. 1B is to add an additional transistor to the output of the voltage down converter in order to supply fluctuating current demands of the memory. However, this solution is not appropriate for embedded memories that have many diverse operations such as single read and write or read or write concurrent with a refresh operation, each type of operation sinking different amounts of current depending on the process, voltage, or temperature variations. Furthermore, the inherent delay of the comparators used in this approach is not sufficient to maintain a steady voltage level in the voltage down converter output. This is especially the situation in memories operating at high frequencies.
Several other conventional VDCs are shown in U.S. Pat. No. 6,806,692 issued to Lee. In such memory devices, a VDC may be used in various applications to supply large amount of “AC” type current (e.g., alternating or fluctuating current) while sustaining the necessary “DC” type current (e.g., a fixed current) and a steady DC voltage level. The conventional VDC design has some drawbacks when employed in modern applications, which often require large, fluctuating output currents. To provide a large current, the VDC will typically require a relatively large source follower transistor. In order to drive such a large transistor, a corresponding comparator has to be relatively powerful. The relatively large transistor and comparator size results in substantial and undesirable current consumption for the VDC. Also, the feedback or coupling capacitor must be relatively large in size to stabilize the VDC. The performance-to-power ratio of this type of conventional VDC diminishes with increasing current supply requirements. In the presence of increasing current demands and high frequencies of operation, the conventional VDC eventually becomes sluggish to supply adequate AC current for digital circuits. When such a scenario occurs, the VDC cannot maintain the output voltage Vpp at a steady level and voltage level dipping occurs. In a DRAM chip, a large dip in voltage level can cause memory cells to fail. Accordingly, there is a need to keep Vpp stable even while the memory device is operated at high frequencies for various operations each requiring high current demands.
The VDC 110 in prior art FIG. 1B includes comparators 170 and 171, a relatively large PMOS (positive channel metal oxide semiconductor) transistor 151 and a relatively small PMOS transistor 152, and a feedback compensation or coupling capacitor Pcc. Comparators 170 and 171 receive two inputs, a reference voltage (Vref) input and feedback loop input (Vfb). The output of the comparator 170 is coupled to the gate of transistor 151 while the output of the comparator 171 is coupled to the gate of transistor 171 and to the gate of transistor 153. Transistor 170 has a high gain but a low speed response to the signal that it receives in its gate, while transistor 171 has a low gain but a high frequency response.
The prior art VDC 110 as shown in FIG. 1B does not operate well for high frequency memories. This is due to the fact that the analog circuit shown by VDC 110 is inherently slow and cannot function well within ever increasing memory speeds where activity on the load is quickly changing. More specifically, the comparator requires a minimum difference between the reference voltage and the feedback voltage in order to change its output and to increase or decrease the current provided to the output node D1.
There is therefore a need for a new and improved voltage down converter for use with high speed memory devices, which can provide relatively large output currents and voltages, which minimizes voltage variations during operation, and which has improved stability and robustness.